FIG. 31 is a circuit diagram showing a phase shift circuit disclosed in U.S. Pat. No. 6,137,377 as a first conventional example.
In the phase shift circuit shown in FIG. 31, a first field effect transistor (hereinafter referred to as “FET”) 1.03 operates as a switch for switching between an on state and an off state, and a first bias terminal 118 is connected to a gate electrode of the first field effect transistor through a first resistor 113.
When a potential same as that of a drain voltage and a source voltage of the FET 103 is applied to the bias terminal 118, the FET 103 turns on and exhibits a resistivity (hereinafter referred to as “on resistance”).
On the other hands, when a gate voltage equal to or lower than a pinch off voltage is applied to the bias terminal 118, the FET 103 turns off and exhibits a capacitivity (hereinafter referred to as “off capacitance”). An FET 104 and an FET 105 operate in the same manner as the FET 103.
A first resistor 113, a second resistor 114, a third resistor 115, a fourth resistor 116, and a fifth resistor 117 have such a sufficiently large resistance that a high frequency signal inputted from a high frequency signal input terminal 101 cannot pass through the resistors.
A voltage (disclosed as −5V in U.S. Pat. No. 6,137,377) equal to or lower than the pinch off voltage is constantly applied to a bias terminal 118 and a bias terminal 120. A voltage of 0 V or equal to or lower than the pinch off voltage is applied to a bias terminal 119.
Subsequently, a description will be given of an operation of the phase shift circuit shown in FIG. 31.
FIG. 32 is an equivalent circuit diagram in which a voltage equal to or lower than the pinch off voltage is applied to the bias terminal 119. In this situation, the FET 103 turns on and exhibits an on resistance 122, and the FET 105 turns off and exhibits an off capacitance 123.
The circuit shown in FIG. 32 can be regarded as a high pass filter (hereinafter referred to as “HPF”) which is composed of a first capacitor 109, a second capacitor 110, a first inductor 106, and a second inductor 107. The HPF causes a signal inputted from the high frequency signal input terminal 101 to have a phase lead, and the signal is then outputted from a high frequency signal output terminal 102.
Also, FIG. 33 is an equivalent circuit diagram in which 0 V is applied to the bias terminal 119. In this situation, the FET 103 turns off and exhibits an off capacitance 124, the FET 104 turns off and exhibits an off capacitance 125, and the FET 105 turns on and exhibits an on resistance 126.
The circuit shown in FIG. 33 can be regarded as a low pass filter (hereinafter referred to as “LPF”) which is composed of the first inductor 106, the second inductor 107, and the off capacitance 125. The LPF causes a signal inputted from the high frequency signal input terminal 101 to have a phase delay, and the signal is then outputted from the high frequency signal output terminal 102.
A difference between the phase lead that is caused by the HPF and the phase delay that is caused by the LPF corresponds to a required phase shift amount. When the voltage of 0 V, or equal to or lower than the pinch off voltage is applied to the bias terminal 119, the signal inputted from the high frequency signal input terminal 101 switches over the respective on/off state of the FET 103, the FET 104, and the FET 105 according to the voltage applied to the bias terminal 119, to thereby obtain a desired phase shift amount, and the signal is outputted from the high frequency signal output terminal 102. In other words, of the bias terminals, the bias terminal 119 is the only one that gives a control signal for switching each of the states of HPF and LPF.
Then, FIG. 34 is a circuit diagram showing a phase shift circuit according to a second conventional example disclosed in IEEE IMS2000 Proceedings, “A Compact 5-Bit Phase Shifter MMIC for K-Band Satellite Communication Systems”.
In the phase shift circuit shown in FIG. 34, a first FET 127 operates as a switch for switching between the on state and the off state, and when a voltage of a potential same as that of a drain voltage and a source voltage of the first FET 127 is applied to a gate terminal of the first FET 127, the first FET 127 turns on, and exhibits the resistivity (hereinafter referred to as “on resistance”). On the other hand, when a voltage equal to or lower than the pinch off voltage is applied to the gate terminal, the first FET 127 turns off and exhibits the capacitivity (hereinafter referred to as “off capacitance”). A second FET 128 also operates in the same manner as the first FET 127.
Subsequently, a description will be given of an operation of the phase shift circuit shown in FIG. 34.
FIG. 35 is an equivalent circuit diagram when the first FET 127 is turned off and the second FET 128 is turned on. A capacity 134 exhibits a synthetic capacity of the off capacitance of the first FET 127 and the capacitor 132, and a resistor 135 exhibits the on resistance of the second FET 128. In this situation, the circuit shown in FIG. 35 can be regarded as a high pass filter (hereinafter referred to as “HPF”) which is composed of a synthetic capacity 134, a first inductor 129, and a second inductor 130. The HPF causes a signal inputted from the high frequency signal input terminal 101 to have a phase lead, and the signal is then outputted from the high frequency signal output terminal 102.
Also, FIG. 36 is an equivalent circuit diagram when the first FET 127 is turned on and the second FET 128 is turned off. A resistor 136 exhibits the on resistance of the first FET 127, and a capacity 137 exhibits the off capacitance of the second FET 128. A parallel circuit composed of the third inductor 131 and the off capacitance 137 enters a parallel resonance state at a desired frequency f0.
In this situation, the circuit shown in FIG. 36 can be regarded as a band pass filter (hereinafter referred to as “BPF”) which allows a high frequency signal in the vicinity of the frequency f0 to pass therethrough when reactances of the first inductor 129 and of the second inductor 130 are sufficiently large. The BPF causes a signal inputted from the high frequency signal input terminal 101 to have a phase changed by substantially 0, and the signal is then outputted from the high frequency signal output terminal 102.
A difference between the phase lead caused by the HPF and the phase change caused by the BPF corresponds to a required phase shift amount. The signal inputted from the high frequency signal input terminal 101 switches between the respective on/off state of the first FET 127 and the second FET 128, to thereby obtain a desired phase shift amount, and is outputted from the high frequency signal output terminal 102.
As described above, the phase shift circuit according to the first conventional example shown in FIG. 31 involves such a problem that a large number of circuit structural elements included in the circuit leads to an increased size thereof.
Also, the phase shift circuit according to the second conventional example shown in FIG. 34 involves such a problem that a phase shift amount that is equal to or higher than 90° is not obtained because the phase circuit has a structure in which the states of the HPF and the BPF are switched. In addition, it is necessary to set a cutoff frequency of the HPF to be lower than a desired frequency band, which leads to such a problem that the circuit is increased in size as the frequency becomes lower. Also, it is necessary to set the cutoff frequency of the HPF to be lower as the phase shift amount becomes smaller, which leads to an increased size of the circuit.
The present invention has been made to solve the above problems, and therefore has an object to provide a phase shift circuit which is downsized and has a broadband characteristic, and a high frequency switch and a phase shifter which are used for the phase shift circuit.